DRAM with reduced-test-time-mode

ABSTRACT

In a semiconductor memory device comprising a plurality of memory cells, a test request detection circuit responds to a voltage, on an input terminal, higher than a range of voltages supplied under ordinary operation condition for producing a test signal. Responsive to the test signal, data which has been supplied to the semiconductor memory device are simultaneously written into a plurality of memory cells, and data are simultaneously read from a plurality of memory cells, and judgement is made as to whether or not the data from the memory cells coincide with the data originally supplied to the semiconductor memory device.

This application is a continuation, of application Ser. No. 939,137,abandoned, filed 12/8/86.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor memory deviceincorporating a field effect transistor, and particularly toimprovements in such a semiconductor memory for shortening the testtime.

The storage capacity of semiconductor memory devices is making rapidprogress: the capacity is quadrupled every 3 years or so. The timerequired for testing the operation of the memory device is increasedwith the increasing storage capacity.

A dynamic RAM of a 1 M words ×1 bit configuration in which the addressesare duplexed and which has been placed on the market is shown in 1985IEEE ISSCC, p. 238, "An 85 ns 1 Mb in a plastic DIP", Yasukazu Inoue, etal., and 1985 IEEE ISSCC, p. 240, "A 90 ns 1 Mb DRAM with Multi-Bit TestMode", Masaki Kumanoya, et al. If, in this dynamic RAM, "0" data iswritten into all the memory cells and "0" data is read out of all thememory cells, and "1" data is written into all the memory cells and "1"data is read out of all the memory cells, and if the cycle time (themaximum pulse width of the RAS (row address strobe)signal) is 10microsec., the test time T1 is given by the following equation (1):##EQU1## With an ordinary dynamic RAM, the above-described test must berepeated for the maximum (5.5 V) and the minimum (4.5 V) voltages of theoperating power source voltage range, and for the highest (70° C.) andthe lowest (0° C.) temperatures of the operating temperature range. Thetotal test time T2 will therefore be as follows:

    T2=40 sec. ×4=160 sec. . . .                         (2)

The test time given by the equation (2) is relatively long as a testtime of an IC, and reduces the productivity.

SUMMARY OF THE INVENTION

An object of the invention is to reduce the test time.

Another object of the invention is to provide a semiconductor memorydevice of which a plurality of memory cells can be concurrently tested,so that the test time can be reduced.

The invention provides a reduced-time test request detection circuitwhich responds to a voltage on at least one input terminal exceeding anormal operating range, and an arrangement by which data is concurrentlywritten into a plurality of memory cells and data is concurrently readout of a plurality of memory cells.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1A-C is a circuit diagram showing an example of a reduced-time testrequest detection circuit of a semiconductor memory device according tothe invention;

FIG. 2A-L is a timing chart showing the operation of the circuit of FIG.1;

FIG. 3 is a timing chart showing in further detail the operation at t1in FIG. 2;

FIG. 4A-B is a circuit diagram showing a semiconductor memory deviceincorporating the reduced-time test request detection circuit of FIG. 1;

FIG. 5A-M is a timing chart showing the operation of the circuit of FIG.4;

FIG. 6 is a schematic view showing, a second embodiment of theinvention; and

FIG. 7A-C is a schematic view showing, in further detail, the embodimentof FIG. 6.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows an examples of a reduced-time test request detectioncircuit forming a part of a semiconductor memory device according to thepresent invention.

In FIG. 1A, there are provided a power source terminal 1 to which apower source voltage Vcc is applied, an external input terminal 2 towhich an external CAS (column address strobe) input signal is applied, aMOST (MOS transistor) 3 having its drain and gate connected to theexternal input circuit 2, a MOST M1 having its drain and gate connectedtogether at a junction N1 and connected to the source of the MOST 3, andseries connection of MOSTs M2 through Mn having their respective drainsand gates connected together at junctions N2 through Nn and connected tothe respective source of the MOSTs M1 through M(n-1). There are alsoprovided a MOST 4 having its drain connected at a junction 5 with thesource of the MOST Mn, having its source connected to the ground, andhaving its gate connected to a terminal 6 to which an internal clocksignal φRAS is applied, a MOST 7 having its drain connected to the powersource terminal 1, and having its gate connected to the terminal 6, aMOST 8 having its drain connected at a junction 9 with the source of theMOST 7, having its source grounded and having its gate connected to thejunction 5, a MOST 10 having its drain connected to the junction 5,having its source grounded and having its gate connected to the junction9, a MOST 11 having its drain connected to a terminal 12 to which aninternal clock signal φRAS is applied, having its gate connected to thepower source terminal 1 and having its source connected to a junction13, a MOST 14 having its drain connected to the power source terminal 1,having its gate connected to the junction 13, and having its sourceconnected to a junction 16, a MOST 15 having its drain connected to thejunction 16, having its source grounded and having its gate connected tothe junction 9, and a capacitance element 17 having one electrodeconnected to the junction 13 and having the other electrode connected tothe junction 16, the MOSTs 11, 14 and 15, and the capacitance element 17form in combination a bootstrap inverter circuit of which the MOST 14serves as a load transistor, the MOST 15 serves as a driver transistor,the MOST 11 serves as a charging transistor and the capacitance element17 serves as a boosting capacitor.

There are further provided a MOST 18 having its drain connected to thejunction 16, having is source connected a junction 19 and having itsgate connected to the power source terminal 1, a MOST 20 having itsdrain connected to a terminal 21 to which an internal clock signal φCASis supplied, having its gate connected to the junction 19 and having itssource connected to a junction 22, a MOST 23 having its drain connectedto the junction 22, having its gate connected to the terminal 6 andhaving its source grounded, a resistor 24 having one end connected tothe power source terminal 1 and having the other end connected to ajunction 26, and a MOST 25 having its drain connected to the junction26, having its gate connected to the junction 22 and having its sourcegrounded.

FIG. 1B shows a circuit for producing internal RAS signals φRAS and φRASwhich are respectively applied to the terminals 12 and 6 shown in FIG.1A.

As illustrated in FIG. 1B, there are provided an inverter circuit 28having its input terminal connected to a terminal 27 to which anexternal RAS (row address strobe) signal is applied, and having itsoutput terminal connected to the terminal 12 identical to the terminal12 of FIG. 1A, and an inverter circuit 29 having its input terminalconnected to the terminal 12, and having its output terminal connectedto the terminal 6 identical to the terminal 6 Of FIG. 1B.

FIG. 1C shows a circuit for producing internal CAS signals φCAS and φCASwhich are respectively applied to the terminal 21 shown in FIG. 1A and aterminal 32.

As illustrated in FIG. 1C, there are provided an inverter circuit 30having its input terminal connected to the terminal 2 and having itsoutput terminal connected to the terminal 21, and an inverter circuit 31having its input terminal connected to the terminal 21 and having itsoutput terminal connected to a terminal 32.

The operation of the circuit of FIG. 1 will be described with referenceto FIG. 2, and FIG. 3 showing in further detail the operation at thetime t1 with an enlarged time scale.

The internal clock signals φRAS, φRAS and φCAS produced from theexternal signals RAS and CAS are respectively shown in FIG. 2C, 2D and2E. The illustration of the internal clock signal φCAS is omitted. Up tothe time t1 the signals on the junctions 5, 13, 16 and 22 are at the "L"level, as shown in FIG. 2F, 2H, 2I and 2K, respectively, while thesignals on the junctions 9 and 26 are at the "H" level, as shown inFIGS. 2G and 2L, respectively.

At the time t2, the external RAS falls to "L", the φRAS rises to "H" andthe φRAS falls to "L", as shown in FIGS. 2C and 2D. The transistor 4 istherefore turned off.

If the number n of the MOSTs M1 through Mn is assumed to be 11 (eleven),the total number of the MOSTs connected in series (having their drainsand source directly connected to each other) between the terminal 2 andthe junction 5 will be 12. If the threshold voltage V_(TH) of the MOSTs3 and M1 through Mn is assumed to be 0.5 V, the series connection of theMOSTs 3 and M1 through Mn is equivalent to a single MOST having athreshold voltage of 0.5×12=6 V and having its drain and gate connectedto the terminal 2 and having its source connected to the junction 5. Ifthe voltage value of the "H" level of the external CAS signal is 5 V,which is the value under the normal operating condition, the "H" levelof the external CAS input is below the threshold voltage (6 V) of theequivalent MOST, which therefore does not conduct so that the states ofthe junctions 5 and 9 do not change. In this state, the memory deviceperforms the normal operation.

If the "H" level of the external CAS input is set at a value, such as 10V, as shown in FIG. 2B, higher than the threshold voltage of theequivalent MOST, the equivalent MOST turns on when the φRAS falls to"L". As the ON resistance of the MOST 10 is set at sufficiently higherthan the ON resistance of the equivalent MOST, the potential on thejunction 5 is increased with the level of the CAS, so that the MOST 8 isturned on. Accordingly, the potential on the junction 9 falls to "L".

As is better illustrated in FIG. 3, the junction 13 is charged at t11,to a voltage Vcc-V_(TH), lower than the power source voltage Vcc by thethreshold voltage V_(TH) of the MOST 11, so that the MOST 14 isconductive. If, in this state, the gate voltage of the MOST 15 fallsfrom "H" to "L" (t12-t13) due to the MOST 8 turning on, the MOST 15 isturned off, and the level of the junction 16 rises from "L" to "H"(t13-14). The voltage increment is transmitted through the capacitor 17and pushes up the level of the junction 13 to a value higher thanVcc+V_(TH), and increases the level of the junction 16 to Vcc. As aresult, the level of the junction 19 is charged up to the voltageVcc-V_(TH) lower than Vcc by the threshold voltage V_(TH) lower than Vccby the threshold voltage V_(TH) of the MOST 18.

At the time t2, the external CAS signal falls to "L", as shown in FIG.2B, and φCAS rises to "H". The MOST 23, with the gate voltage being at"L", is nonconductive. The MOST 20 is conductive. As φCAS rises from "L"to "H", the potential at the junction 19 is pushed up, by virtue of thegate capacitance of the MOST 20 as shown in FIG. 2J, to Vcc+V_(TH). Thelevel of a test signal TEST on the junction 22 rises, as shown in FIG.2K, to Vcc. As the potential level on the junction 22 rises, the MOST 25turns on, and, as shown in FIG. 21, the level of the test signal TEST onthe junction 26 falls from "H" to "L". Thus, the test signal TEST risesto "H" and the test signal TEST falls to "L".

At the time t3, the external RAS rises to "H", and φRAS falls to "L" andφRAS rises to "H". In this state, the signals on the junctions 5, 13, 16and 22 fall to "L", while the signals on the junction 9 and 26 rise to"H". Thus, the test signal TEST falls to "L", and the test signal TESTrises to "H". The test time shortening state is thereby terminated.

An example of a circuit for generating a test signal for bringing aboutthe test time shortening state has been described with reference toFIGS. 1 and 2. Now the memory using the test signal for shortening thetest time will be described.

For simplicity of description, it is assumed that a semiconductor memoryhaving a storage capacity of 4 bits, shown in FIG. 4, is taken as anexample. The semiconductor memory comprises only 8 terminals or pins,namely an address input terminal on which the addresses are duplexed,and the terminals for RAS, CAS, R/W, D_(IN), D_(OUT), a power source andthe ground.

As illustrated in FIG. 4, there are provided memory cells 41a through41d of one bit, and reading amplifiers 42a through 42d connected atjunctions 43a through 43d with the memory cells 41a through 41d andamplifying data read out of the memory cells. The amplifiers are shownto have only one stage, but commonly two-stage amplifiers are used.There are also provided MOSTs 45a through 45d connected between ajunction 54 and junctions 44a through 44d, and having their gatesconnected to junctions 47a through 47d. MOST 46a through 46d connectedbetween the junction 54 and the junctions 44a through 44d and havingtheir gates connected to the terminal 22, and MOSTs 49a through 49dconnected between junctions 48a through 48d and a junction 55, andhaving their gates connected the junctions 47a through 47d.

There are further provided an external data input terminal 50 to whichan external data input is supplied, an output terminal 51 through whichan output data is read out, an input buffer 52 having its input terminalconnected to the terminal 50 and having its output terminal connected tothe junction 54, the activated at the time of writing, a MOST 56connected between the junction 55 and a junction 57 and having its gateconnected to the terminal 26, a MOST 58 connected between the junction57 and a junction 62 and having its gate connected to the junction 22,and an output buffer 59 having its input terminal connected to thejunction 57 and having its output terminal connected to the terminal 51.

There are further provided an input terminal 60 to which an addressinput is supplied, and a decoder 61 having two-bit address input andhaving four-bit output. Exclusive-OR circuits 66a through 66d, eachhaving one input connected to a respective one of the junctions 48athrough 48d, and having the other input connected to a junction 65, afour-input OR circuit 68 having its inputs connected to the outputs ofthe Exclusive-OR circuits 66a, through 66d, and an input buffer 63having its input connected to the terminal 50 and having its outputconnected to the junction 65, and activated at the time of reading.

As is shown in FIG. 4B, there are further provided an input terminal 70to which an R/W input signal is applied, an input buffer 71 connectedbetween the input terminal 70 and the junction 53, also shown in FIG.4A, to produce a write signal W, and an input buffer 72 connectedbetween the junction 53 and 64, to produce a read signal R.

The operation of the circuit of FIG. 4 will now be described withreference to FIG. 5, which illustrates the operation during writing.

When data is written in, the R/W signal shown in FIG. 5D is set at "0".At the time t1, RAS shown in FIG. 5A falls, when the row address of theduplexed address signal A shown in FIG. 5C is taken in by the decoder61.

At the time t2, the column address is taken in. Depending on the statesof the row address and the column address, one of the four decoderoutput is set at "1". As an example, the output signal on the junction47a is shown to be at "1", while the signals on the junctions 47athrough 47d are shown to be at "0", as shown in FIGS. 5H through 4K.Accordingly, the MOST 45a is conductive, while the MOST 45b through 45dare nonconductive. The write signal W shown in FIG. 5C is set at "1", asa result of which the input buffer 52 is activated and the data inputD_(IN) shown in FIG. 5E is transmitted to the junction 54, and is thentransmitted through the MOST 45a, now conductive, and written in thememory cell 41a.

The above description is on ordinary operation which takes place whenthe "1" level of CAS is at about 5 V. If the "0" level of CAS is raisedto 10 V, as shown by a broken line in FIG. 5B, the test signal TESTshown in FIG. 5L becomes "1" and the test signal TEST shown in FIG. 5Mbecomes "0", as was described with reference to FIGS. 1 and 2. In thisstate, the MOSTs 46a through 46d are all made conductive, so that thesame data on the junction 54 is concurrently written in all the memorycells 41a through 41d. This means that the time required for writing isreduced to 1/4 (one fourth) compared with a situation where the MOSTs45a through 45d are made conductive in turn and the writing into thememory cells 41a through 41d are made in turn.

During reading, the R/W signal is set at "1" and the R signal shown inFIG. 5G is set a "1". As a result, the input buffer 63 is activated, andthe input signal D_(IN) supplied to the input terminal 50 is transmittedto the junction 65.

The data read out of the memory cells 41a through 41d are amplified bythe amplifiers 42a through 42d and transmitted to the junctions 48athrough 48d. These data are compared with the input data D_(IN) at theExclusive-OR circuits 66a through 66d. The outputs of the Exclusive-ORcircuits 66a through 66d are at "0" or at "1", depending on whether ornot the data from the memory cells 41a through 41d are coincident withthe input data D_(IN). If any of the Exclusive-OR circuits 66a through66d produces "1" reflecting the fact that the data from thecorresponding memory cell is not coincident with the input data D_(IN),the output of the OR circuit 68 becomes "1". Thus, the data from thefour memory cells 41a through 41d can be simultaneously checked. Thetest time is therefore reduced to 1/4.

The circuit comprising MOSTs 56 and 58 constitute a switch between anordinary operation mode and a reduced test tie operation mode. In theordinary operation mode, the MOST 56 is made conductive, and the datafrom the memory cell selected by the output of the decoder 61 istransmitted to the output buffer 59.

In the reduced test time operation mode, the MOST 58 is made conductive,so that the output of the OR circuit 68 is transmitted to the outputbuffer 59, and hence to the output terminal 51. It is therefore possibleto make judgement on the memory cell data from the data on the outputterminal 51. That is, "1" on the output terminal 51 reflects presence ofan error, while "0⃡ reflects absence of an error.

In the embodiment described, the "1" level of the CAS input is raisedfor producing the test signals TEST and TEST. The invention is notlimited to such an arrangement. That is, "1" level of any other inputsignal may alternatively be raised during the period when the R/W signaland the D_(IN) signal are in an arbitrary state.

A second embodiment of a semiconductor memory according to the inventionwill now be described with reference to FIG. 6.

The semiconductor memory device of this embodiment of the inventioncomprises a memory cell array 80 having 262,244 memory cells arranged in512 (=2⁹) rows and 512 (=2⁹) columns to form a matrix. The memory cellarray 80 is divided into four blocks 85 through 88, each block having262,144/4= 65,536 memory cells. Denoted by numerals 81 through 84 areunit memory cells of a single bit occupying the same positions withinand with respect to the respective blocks 85 through 88.

To select one memory cell within the memory cell array 80, 9 bits (RA0through RA8) for a row address signal and 9 bits (CA0 through CA8) for acolumn address signal i.e., 18 bits in all are needed. If, however, fourmemory cells, e.g., 81 through 84 are simultaneously selected, the mostsignificant bits (RA8 and CA8) of the column address signal and the rowaddress signal are not necessary. This facilitates realization of thesecond embodiment. Dynamic RAMs which are widely manufactured today havea system where each bit of the row address signal and a correspondingbit of the column address signal are supplied, using a time-sharingtechnique, through a single input terminal. For instance, the dynamicRAM shown in FIG. 6 has 9 address input terminals A0 through A8, throughwhich 9 bits RA0 through RA8 of the row address signal are supplied andthen 9 bits CA0 through CA8 of the column address signal are supplied.

When the four memory cells are to be simultaneously selected, theterminal A8 is not necessary for the purpose of supplying an addresssignal. It is therefore possible use the terminal A8 to apply a high DCvoltage for generating the test signals. In this embodiment, it is onlynecessary to apply a high DC voltage, so that the circuit arrangement issimpler than the example of FIG. 1 where the "1" level of CAS needs tobe raised.

FIGS. 7A, 7B and 7C illustrate in further detail how the concept of theembodiment of FIG. 6 is implemented. For simplicity of illustration anddescription, the memory cell array 80 is shown to comprise only 64memory cells MC11 through MC88 arranged in 8 rows and 8 columns. Thearray is divided into four blocks 85, 86, 87, and 88, each comprising 16memory cells arranged in 4 rows and 4 columns. All the bit lines of eachblock are connected through a respective one of transfer gates TG11through TG28 to a respective one of the 4 lines or nodes 44a through44d.

To select one of the memory cells, 3 bits (RA0 through RA2) for a rowaddress signal and 3 bits (CA0 through CA2) for a column address signalare inputted. The MSB (RA2) of the row address signal and the MSB (CA2)of the column address signal are supplied to the decoder 61, whichthereby selects on of the lines 44a through 44d. The remaining bits(RA1, RA0) of the row address signal are supplied to a row decoder, notshown, to select one of the lines WT0 through WT3 thereby selecting oneof the word lines in each block. The remaining bits CA1, CA0) of thecolumn address signal are supplied to a column decoder, not shown, toselect one of the lines BD0 through BD3 thereby selecting one of the bitlines in each block. The bit lines are respectively connected toamplifiers 42.

During an ordinary operation, four memory cells, e.g. MC11, MC15, MC51,MC55, at the same position within the respective blocks are selected bythe outputs of the row address decoder and the column address decoder,and one of the four memory cells are selected by the outputs of thedecoder 61.

When a reduced-time test is to be conducted the MSBs of the row addresssignal and the column address signal are not supplied and instead a highDC voltage commanding the test is inputted through the address terminalA2 for the MSBs (RA2, CA2). This high DC voltage is detected by areduced-time test request detection circuit 100, by which the testsignals TEST and TEST are produced, and all of the four memory cellsselected by the row address decoder and the column address decoder areconcurrently accessed.

As has been described, according to the invention, a plurality of memorycells are simultaneously tested by raising above the range of the levelssupplied under ordinary operation condition, the level of one of theinput signals. The test time can therefore be reduced. This reduction inthe test time does not require increase in the number of terminals.

What is claimed is:
 1. A semiconductor memory device, comprising:aplurality of address lines, a plurality of memory cells coupled withsaid address lines, a test request detection circuit means to produce atest signal if a voltage has been applied on a most significant one ofsaid address lines which is higher than a range of voltages suppliedunder ordinary operation conditions, means responsive to the test signalfor causing writing of data, which has been supplied to thesemiconductor memory device, into a plurality of memory cellssimultaneously, and thereafter, simultaneously reading data from saidplurality of memory cells, and means for judging whether or not the dataread from said plurality of memory cells coincides with the dataoriginally supplied to the semiconductor memory device.
 2. A deviceaccording to claim 1, wherein said judging means comprises a pluralityof judging circuits receiving the data having been supplied to thesemiconductor memory device and the data read out of the respectivememory cells.
 3. A device according to claim 2, wherein each of thejudging circuits comprises an Exclusive-OR circuit whose output is at"1" if the data read out of the corresponding memory cell does notcoincide with the data having been supplied to the semiconductor memorydevice.
 4. A device according to claim 3, wherein said judging meansfurther comprises an OR circuit receiving the output of the Exclusive-ORcircuit to produce an error detection signal if any of the Exclusive-ORcircuit produces an output of "1".
 5. A device according to claim 2,wherein said judging means outputs results indicating whether data readout from ones of the memory cells coincides with data originallysupplied to the semiconductor memory device onto an external terminal.6. A device according to claim 1, wherein each of the memory cellscomprises a field effect transistor.
 7. The memory of claim 1, whereinsaid memory is a dynamic random access memory (DRAM).
 8. The memory ofclaim 1, wherein said test request detection circuit contains pluralFETs connected together to provide an effective threshold voltage whichis outside of the range of voltages supplied under ordinary operationconditions.
 9. A semiconductor memory device, comprising:at least onearray of memory cells coupled with said address lines; peripheral logicconnected to select ones of said memory cells for reading or writing inaccordance with externally received cell address signals, wherein onesof said cell address signals are sequentially multiplexed onto a set ofaddress lines which are less than the number needed to uniquely identifyone of said cells; a test request detection circuit means to produce atest signal if a voltage has been applied on a most significant one ofsaid address lines which is higher than a range of voltages suppliedunder ordinary operation conditions; a parallel addressing circuit,which causes said peripheral logic to write externally supplied datainto a plurality of said memory cells simultaneously, when said testdetection circuit indicates that a high voltage has been received; andat least one judging circuit, which ascertains whether a memory cell hascorrectly repeated the data value which was stored in it.
 10. Asemiconductor memory device, comprising: a plurality of subarrays ofmemory cells;peripheral logic connected to select ones of said memorycells for reading or writing in accordance with externally received celladdress signals, wherein ones of said cell address signals aresequentially multiplexed onto a set of address lines which are less thanthe number needed to uniquely identify one of said cells; a test requestdetection circuit means to produce a test signal if a voltage has beenapplied on a most significant one of said address lines which is higherthan a range of voltages supplied under ordinary operation conditions; aparallel addressing circuit, which causes said peripheral logic to writeexternally supplied data into a plurality of said memory cells, inplural respective ones of said subarrays, simultaneously, at locationsdetermined by data on the ones of said address lines on which saidvoltage was not applied, when said test detection circuit indicates thata high voltage has been received; and at least one judging circuit,which ascertains whether a memory cell has correctly repeated the datavalue which was stored in it.
 11. The memory of claim 9, wherein saidtest request detection circuit contains plural FETs connected togetherto provide an effective threshold voltage which is outside of the rangeof voltages supplied under ordinary operation conditions.
 12. The memoryof claim 10, wherein said test request detection circuit contains pluralFETs connected together to provide an effective threshold voltage whichis outside of the range of voltages supplied under ordinary operationconditions.
 13. The memory of claim 9, wherein said parallel addressingcircuit causes said peripheral logic to write externally supplied datainto a plurality of said memory cells at locations determined by data onones of said address lines on which said voltage was not applied. .Iadd.14. A semiconductor memory device, comprising:(a) a plurality of addresslines; (b) a plurality of memory cells coupled with said address lines;(c) a test request detection circuit means to produce a test signal uponreceipt of a higher voltage which is higher than a range of voltagesapplied under ordinary operation conditions, said test request detectioncircuit means comprising(i) an input terminal for receiving said highervoltage, (ii) a series connection of a plurality of MOSTs, each having agate and a drain, wherein said series connection of MOSTs is connectedat a first end to said input terminal, and wherein each of said MOSTshas its gate and drain coupled together, (iii) a latch circuit, coupledto a second end of second series connection of MOSTs at a first end ofsaid latch circuit, (iv) an inverted test signal generating circuitresponsive to an output end of said latch circuit, wherein said testsignal generating circuit produces an inverted test signal, and (v) areset circuit for resetting said latch circuit; (d) means responsive tothe test signal for causing writing of data, which has been supplied tothe semiconductor memory device, into a plurality of memory cellssimultaneously, and thereafter, simultaneously reading data from saidplurality of memory cells; and (e) means for judging whether or not thedata read from each of said plurality of memory cells coincides with oneanother. .Iaddend. .Iadd.
 15. The semiconductor memory device of claim14, wherein said latch circuit comprises two MOSTs cross-coupled witheach other, wherein each of said MOSTs contain a gate, and wherein thegate of one of said MOSTs is coupled to said second end of said seriesconnection of MOSTs. .Iaddend. .Iadd.16. The semiconductor memory deviceof claim 15, wherein said reset circuit comprises at least one MOSTwhich couples the gate of at least one of said two MOSTs to a powersupply node. .Iaddend. .Iadd.17. A semiconductor memory device,comprising:at least one array of memory cells coupled with said addresslines; peripheral logic connected to select ones of said memory cellsfor reading or writing in accordance with externally received celladdress signals, wherein ones of said cell address signals aresequentially multiplexed onto a set of address lines which are less thanthe number need to uniquely identify one of said cells; a test requestdetection circuit means to produce a test signal if a voltage has beenapplied on a most significant one of said address lines which is higherthan a range of voltages supplied under ordinary operation conditions; aparallel addressing circuit responsive to the test signal for causingsaid peripheral logic to write externally supplied data into a pluralityof said memory cells simultaneously; and at least one judging circuit,which ascertains whether said plurality of memory cells have correctlyrepeated the data value which was stored in them.